FIG. 1 shows a schematic diagram of an integrating circuit commonly used in a dual slope integrating analog-digital converter having at least the following four modes of operation: integrate, deintegrate, zero-integrate, and X10 modes.
During the integrate mode, an analog input voltage Vin is applied to an input terminal 110 for a fixed period of time. A timing and control circuit 115 closes switch SW1 and opens switch SW2. In this example, Vin is equal to V.sub.l, which is a positive voltage. A buffer circuit 120 receives input voltage Vin and outputs a voltage Vbuf at a node 122, which is substantially equal to voltage V.sub.1. An integrator circuit 130 receives voltage Vbuf and generates a voltage V.sub.INT at a node 136 and, consequently, a voltage V.sub.B at a node B, according to the equation: ##EQU1## where Rint is the value of a resistor 131, Cint is the value of feedback capacitor 134 in parallel with capacitor C2, and Vin(0) is the initial voltage across feedback capacitor 134 and capacitor C2. The effect of capacitor C1 is negligible because switch SW1 "shorts out" capacitor C1.
FIG. 2 shows a diagram of the voltage output of the integrator in the integrating circuit of FIG. 1 during the integrate and deintegrate modes. Curve 210 represents the voltage Vbuf supplied to the input of integrator circuit 130. During time period T1 (integrate mode), voltage Vbuf is substantially equal to V.sub.1 as shown by segment 211 of curve 210. Curve 220 represents the voltage V.sub.INT in response to voltage Vbuf. Because voltage Vbuf is constant during time period T1, voltage V.sub.INT is linear as shown by segment 221 of curve 220.
Referring back to FIG. 1, during the deintegrate mode, timing and control circuit 115 controls switch SW1 to remain closed and switch SW2 to remain opened. The value of voltage Vin applied to input terminal 110 is forced to be equal to -V.sub.ref, which is of opposite polarity from voltage V.sub.1. The voltage -V.sub.ref is obtained by charging a reference capacitor (not shown) with voltage V.sub.ref supplied by a voltage reference (not shown) and then coupling the reference capacitor's negative electrode to input terminal 110 and coupling the reference capacitor's positive electrode to the source of ground potential. As a result, capacitors C2 and 134 begin to discharge and voltage V.sub.B increases at a predetermined fixed slope as shown by segment 222 of curve 220 (FIG. 2).
Also at the beginning of the deintegrate mode, timing and control circuit 115 in a digital section 190 generates clock pulses received by a counter 194. Amplifier 150 receives voltage V.sub.B at a positive input lead 152 and compares it to the voltage at a negative input lead 154. The voltage at negative input lead 154 is substantially equal to ground potential because negative input lead 154 is coupled to the negative input lead of amplifier 132, which is a "virtual ground" due to the operation of integrating circuit 130. When voltage V.sub.B is lower than ground potential, amplifier 150 generates a negative voltage output signal at a node 160, which is coupled to the positive input lead of comparator 170. Comparator 170 generates a logic "zero" signal as voltage Vout at output node 180, which is coupled to digital section 190. Comparator 170 continues to generate a logic "zero" until voltage V.sub.B becomes positive, and then outputs a logic "one". In response to this logic "one" signal, timing and control circuit 115 stops counter 194 and causes voltage Vin to equal 0 V. Thus, counter 194 counts the number of clock pulses needed to completely discharge feedback capacitor 134 (i.e., the time needed for the signal generated at output terminal 180 to reach to a logic "one"). The value of counter 194 is proportional to the voltage level of voltage Vin, and thus the output of counter 194 represents the value of analog voltage Vin in digital form.
The zero-integrate mode is used to completely discharge feedback capacitor 134 after an input signal overrange during the deintegrate mode (i.e., counter 194 has reached its maximum value before the end of the deintegrate mode). During the zero-integrate mode, timing and control circuit 115 controls switches SW1 and SW2 to be closed, which causes integrator 130 to be cascaded with an RC filter formed by the "on" resistance Ron of switch SW1 and capacitor C2. As stated above, the effect of capacitor C1 is negligible because switch SW1 "shorts out" capacitor C1.
On the occurrence of a positive input overrange, voltage V.sub.B at node B is negative. As a result, during the zero-integrate mode, amplifier 150 generates a negative output voltage at a node 160. Buffer 120 receives this negative voltage via switch SW2, which causes integrator 130 to ramp up the voltage at node B, thereby decreasing the absolute value of voltage V.sub.B. When voltage V.sub.B reaches ground potential, the output voltage of amplifier 150 is substantially 0 V and feedback capacitor 134 is fully discharged.
The X10 mode is used to multiply the residual charge of capacitor C2 by -10 to achieve greater resolution in the digital output of the A/D converter. During the X10 mode, timing and control circuit 115 opens switch SW1 and closes switch SW2. FIG. 3 shows a timing diagram of the output of the integrator in the integrating circuit of FIG. 1, wherein curve 305 represents the clock pulses generated by timing and control circuit 115. As stated above, the deintegrate mode ends when voltage V.sub.B is substantially equal to 0 V and timing and control circuit 115 causes voltage Vin to be 0 V to end the deintegrate mode.
However, voltage V.sub.B will typically reach 0 V at some point within a clock period of the timing and control circuit's clock signal 305. In this example, the voltage VB reaches 0 V at a point 301 in a clock period 311. As a result, integrator circuit 130 will continue to deintegrate until the end of clock period 311. Consequently, voltage V.sub.B will rise above 0 V, resulting in a positive residual voltage Vres across capacitors 134 and C2.
The value of counter 194 up to clock period 311 is used to display the value of voltage Vin. However, the counter's value will result in larger value than the true value of voltage Vin. The residual voltage Vres is used in the X10 mode to gain more resolution as follows.
Capacitors C1 and C2 are designed so that the capacitance C2* of capacitor C2 is ten times greater than the capacitance C1* of capacitor C1. EQU C2*=10 C1* (1)
During the X10 mode, timing and control circuit 115 opens switch SW1 and closes switch SW2. Amplifier 150 senses the residual voltage across capacitor C2 and feeds back a positive voltage to the input of integrator 130 via switch SW2 and buffer 120. As a result, integrator 130 begins to decrease the voltage at node 136, which in turn begins to reduce voltage V.sub.B (i.e., the residual voltage across capacitor C2). Because of the negative loop from the output of amplifier 150 to the input of integrator 130, integrator 130 will continue to decrease the voltage at node 136 until voltage V.sub.B is equal to substantially 0 V. The voltage at node 136 is determined as follows.
At the end of the deintegrate mode (i.e., the start of the X10 mode), the charge stored by capacitor C2 is: EQU Q(0)=C2* * Vres (2)
where Q(0) is the residual charge initially stored by capacitor C2 at the start of the X10 mode.
Because capacitors C1 and C2 are connected in series and the voltage across capacitor C1 is zero, charge Q(0) is transferred to capacitor C2 to force voltage V.sub.B to be 0 V. Thus, when voltage V.sub.B reaches 0 V, capacitor C1 stores charge substantially equal to negative Q(0). At this point, the voltage across capacitor C1 is: ##EQU2## where V.sub.C1 is the voltage across capacitor C1.
Combining equations (1), (2), and (3) when voltage V.sub.B is substantially equal to 0 V results in EQU V.sub.C1 =-10 Vres (4)
Consequently, because voltage V.sub.C2 is substantially equal to 0 V, the voltage across capacitor 134 is also negative 10 Vres. Then integrating circuit 100 enters a second deintegrate mode, where timing and control circuit 115 closes switch SW1 and opens switch SW2. As a result, with capacitor C1 "shorted out", charge from capacitors C1 and 134 redistribute between capacitors C2 and 134 until the voltage across capacitor C2 is equal to the voltage across capacitor 134. Capacitor 134 is designed to be much larger than capacitor C2 so that very little charge is redistributed to make the capacitor voltages equal. Thus, at the start of the second deintegrate cycle, voltage V.sub.B remains approximately equal to -10 Vres.
At the end of the second deintegrate cycle, the value of counter 194 represents approximately negative ten times the residual voltage. This value is then divided by -10 and the result added to the first deintegrate value to determine a more accurate value for voltage Vin.
Further, a second residual voltage results from the second deintegrate mode. A second X10 mode, followed by a third deintegrate mode, may be repeated to determine a still more accurate value for voltage Vin. At the end of the third deintegrate mode, the value of counter 194 represents approximately 100 times the residual voltage (i.e., -10 * -10) the second residual voltage. This value is then divided by 100 and the result added to the result from the previous X10/deintegrate cycle to determine a more accurate value for voltage Vin.
FIG. 4 shows a series of two X10 mode/deintegrate modes following an integrate mode/deintegrate mode. In this example, the A/D converter is designed to have a 0.4 V full scale with a 4000 count reading. Thus, each clock period represents a hundredth of a volt. Consequently, when voltage Vin is equal to 0.1234 V, at the end of the first deintegrate mode represented by curve 410, counter 194 will have a value of 13 (which represents 0.13 V), with Vres approximately equal to 0.0066 V. At the end of the first X10 mode represented by curve 415, voltage V.sub.B is approximately equal to 0.066 V. Consequently, at the end of the second deintegrate cycle represented by curve 420, the value of counter 194 is 7 (which represents 0.07 V) with a Vres approximately equal to 0.004 V. Following the second X10 mode represented by curve 425, voltage V.sub.B is approximately equal to 0.04 V. As a result, after the third deintegrate cycle represented by curve 430, the value of counter 194 is 4.
The value of voltage Vin is calculated by dividing the first X10 mode value by "-10" and the second X10 mode value by "100" to account for the added gain during the X10 mode(s), and then adding the result to the first deintegrate mode value. For this example, the result is: EQU Vin=0.13 V+0.07*(1/-10)+0.04*(1/-10) (1/-10) Vin=0.13 V-0.007 V+0.0004 V Vin=0.1234
In this example, capacitor C2 was designed to be ten times capacitor C1 so that a decimal value of voltage Vin is easily computed as shown above. If the value of voltage Vin is desired in a different base, a different ratio between capacitors C1 and C2 can be used. For example, if it is desired to calculate the value of voltage Vin in octal (base 8), then capacitor C1 can be designed to be eight times the value of capacitor C2.
When input voltage Vin is negative, integrating circuit 100 operates in a similar manner as described above for a positive voltage Vin, except that all the polarities are reversed. The operation of integrating circuit 100 receiving a negative Vin is seen by "flipping" each of FIGS. 2-4 about the horizontal time axis. Thus, during the deintegrate mode, a positive voltage V.sub.ref is applied to input terminal 110 so that voltage V.sub.B is ramped down and counter 194 measures the time for voltage V.sub.B to reach 0 V. During the X10 mode, a negative Vres results, which is multiplied by "-10" to generate a positive V.sub.B, which is deintegrated to determine negative ten times the residual voltage. The X10 mode is repeated to determine the "residual of the residual" for a more accurate measurement.
For this circuit to be stable, the gain of amplifier 150 must be limited such that the total loop gain is 0 dB or less where the phase shift introduced at node B is equal to -180.degree. (discussed below in conjunction with FIG. 6). Thus, defining Gamp.sub.150 as the gain of amplifier 150 and Gba as the gain from input terminal 110 to the positive input of amplifier 150, then as a condition for stability during zero-integrate mode, we must have: EQU Gamp.sub.150 +Gba&lt;0 dB EQU Because Gba is negative and Gamp.sub.150 is positive, this equation becomes: EQU Gamp.sub.150 &lt;.vertline.Gba.vertline. (5)
where .vertline.Gba.vertline. is the absolute value of gain Gba.
This leads to a dilemma. It is desirable to improve the performance of integrating circuit 100 by decreasing the time that integrating circuit 100 requires to perform the X10 mode. One solution to increase performance has been to increase the gain in amplifier 150 to more quickly charge capacitors 134 and C1 to negative ten times the voltage Vres. However, for stability in the zero-integrate mode, the gain of amplifier 150 is limited according to equation (5). Therefore a circuit which allows a designer to use a high gain amplifier in the X10 mode without the danger of oscillation will be highly useful.